New CML latch structure for high speed prescaler design - Electrical ...
Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For High Frequency Applications with EDA Tool
Electronics | Free Full-Text | A 0.00426 mm2 77.6-dB Dynamic Range VCO-Based CTDSM for Multi-Channel Neural Recording
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
PDF] Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For High Frequency Applications with EDA Tool | Semantic Scholar
Model and Design of Bipolar and MOS Current-Mode Logic: CML, ECL and SCL Digital Circuits - PDF Free Download
PDF] Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For High Frequency Applications with EDA Tool | Semantic Scholar
Current-Mode-Logic (CML) Latch | EveryNano Counts
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PDF) Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
PDF] Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For High Frequency Applications with EDA Tool | Semantic Scholar