Figure 5.21 from Cmos Logic and Current Mode Logic 5.1 Introduction | Semantic Scholar
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
High Speed Digital Blocks
Used CML circuit cell (divided-by-2) with master and slave D-type flip-flop | Download Scientific Diagram
PDF) Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
CML based DFF combined with NAND function used in 4/5 prescaler block | Download Scientific Diagram
Figure 16.23 from Direct-coupled Fet Logic (dcfl) @bullet Source-coupled Fet Logic (scfl) @bullet Advanced Mesfet/hemt Design Examples Iii-v Hbt for Circuit Designers @bullet Current-mode Logic @bullet Emitter-coupled Logic @bullet Ecl/cml Logic Examples @
DFF-based CMOS clock divider. | Download Scientific Diagram
A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider: Ravindran Mohanavelu and Payam Heydari | PDF
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
Current-Mode-Logic (CML) Latch | EveryNano Counts
Performance evaluation of the low-voltage CML D-latch topology - ScienceDirect
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
4-bit Counter Using High-Speed Low-Voltage CML D-Flipflops | Semantic Scholar
MIPI homepage CMOS prescaler basics
An improved current mode logic latch for high‐speed applications
Low Power Rail to Rail D Flip-Flop Using Current Mode Logic Structure
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
High speed CML latch using active inductor in 0.18μm CMOS technology | Semantic Scholar
